Network Processors

Access Processing Semiconductors for Wireless and Wireline Infrastructure
  • Multiple families of single chip, highly integrated access processors with on-board control and data-path cores
  • Industry standard I/O's from 1.5 Mbps to 10 Gbps are coupled with production quality data-path software for rapid development of access infrastructure designs
  • Universal front end pre-conditioning co-processors supporting rates from DS0 to 4xOC-12/STM-4


WinPath1™ Family First generation access packet processor. Uses up to 4 protocol engines and single MIPS 5Kc core both running up to 233 MHz
WinPath2™ Family Second generation access packet processor. Utilizes up to 6 protocol engines at 350 MHz and has an integrate MIPS 24Kc core running at 600 MHz
WinPath2-Lite Family Derivative of the WinPath2 for cost sensitve designs. 6 protocol engines running up to 300 MHz
WinPath3 Family Latest in WinPath family of devices with up to 12 protocol processors running at 450 MHz, 10 GB ethernet ports and dual MIPS 34Kc cores running at 650 MHz
WinPath3-SuperLite Family Lower cost derivative of WinPath3. The WP3-SL has 6 packed processors at 400 MHz and a single MIPS 34Kc in a smaller package than the WP3
UFE3 Family High channel denisty co-processor for WinPath2 based designs. Full support for OC-12 based solutions down to DS0 granularity
UFE412 Pre-conditioning co-procesor for WinPath3 based designs. Scales to 4xOC-3/STM-1 rates
UFE448 Pre-conditioning co-procesor for WinPath3 based designs. Full APS 1+1 redundancy up 4 OC-12/STM-4 rates
 

News

  • Asidua's Carrier Ethernet Protocol Stack selected by NEC for its LTE Platform
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  • PMC-Sierra Mobile Backhaul Product Receives 2011 NGN Leadership Award
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  • Timesys enables LinuxLink support for PMC-Sierra WinPath3-SuperLite System on Chip
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  • PMC-Sierra Introduces Universal Front End 4 (UFE4) Silicon to Accelerate Transition of Carrier Networks to Ethernet-Based Mobile Backhaul
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  • PMC-Sierra Completes Acquisition of Wintegra
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Awards
 
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